The present invention relates to a CMOS integrated circuit and to a process for producing electric isolation zones in such an integrated circuit. It more particularly applies to the fields of electronics and data processing for in particular obtaining logic gates, flip-flops, read-only and random-access memories, etc.
The desire to obtain a high integration density in CMOS integrated circuits makes it necessary to use a special isolation procedure between the different components of said circuits, and particularly between the n-channel transistors and the p-channel transistors of said CMOS circuits, when it is wished to reduce the distance between the complementary transistors.
One of the recent isolation methods used for this purpose is based on the formation of trenches in the semiconductor substrate, which are then oxidized and filled with a material such as polycrystalline silicon or silicon oxide. The trenches are filled by the deposition of the filling material over the entire surface of the integrated circuit, followed by the removal of the excess of said material deposited outside the trenches. This excess can be removed by mechanical or plasma etching. Generally, above the trench is then formed a local field oxide.
This procedure of isolation by trenches surmounted by a local field oxide has in particular been described in the IEDM article, 1982, pp. 237 to 240, entitled "Deep trench isolated CMOS devices".
This isolation method makes it possible to reach considerable isolation depths (several .mu.m) between the different components of the integrated circuits whilst ensuring a good surface isolation. Unfortunately, in such an isolation method, the problem arises of a conductivity inversion on the sides of the isolation trenches and consequently of the formation of a parasitic channel. This parasitic conductivity inversion problem is particularly described in the IEDM article, 1983, pp. 23 to 26 entitled "Characterization and modeling of the trench surface inversion problem for the trench isolated CMOS technology" of Kit. M. Cham, et al, and makes it necessary to remove the transistors from the isolation trenches and more specifically the n-channel transistors of the CMOS circuit, thus limiting the integration density of said integrated circuits.
This is illustrated in FIGS. 1 and 2, which diagrammatically show in plan view and longitudinal section, part of a prior art CMOS integrated circuit at an isolation trench. In FIGS. 1 and 2, references 52 and 54 respectively represent the regions Occupied by a p-channel transistor and a n-channel transistor. These two transistors are e.g. produced in the same p-silicon, substrate 56, reference numeral 58 corresponding to a n-type recess in which the p-channel transistor is formed. These two transistors are electrically isolated from one another by an isolation trench 60 formed in the substrate. The sides and bottom of trench 16 are covered with an oxide film 62 and the interior of the trench is filled with a more particularly isolating material 64. Isolation trench 60 is surmounted by a field oxide 66. Reference numeral 68 corresponds to the generally doped polycrystalline silicon conductive coating, in which the gates of the two transistors are formed.
As shown in FIGS. 1 and 2, transistors 52 and 54 are necessarily located at a certain distance d from the isolation trench 60 in order to prevent the formation of a parasitic channel due to conductivity inversion on the sides of the trench. The region separating the trench from the transistors being a field oxide region 66 (FIG. 1).